1. Field of the Invention
The present invention relates to a Fin-type channel transistor and a method of manufacturing the same.
2. Background Art
In order to improve the performance of semiconductor integrated circuits, it is necessary to improve the performance of field effect transistors constituting each semiconductor integrated circuit. So far, the device performance has been improved by miniaturizing the devices. However, some point out the limitations of this method. Countermeasures to short channel effect and a decrease in parasitic resistance are considered to be serious problems. According to the International Semiconductor Roadmap, a plurality of new breakthrough techniques would be required to solve such problems in the 45 nm generation or later.
Under such a circumstance, an FD (Fully-Depleted) device, in which the channel region is fully depleted, is expected to constitute a basic device structure in the next generation because of its immunity to the short channel effect. In particular, attention is being given to a transistor using a thin film SOI (Silicon On Insulator) substrate and a Fin-type channel transistor (hereinafter referred to as “FinFET”).
As a countermeasure to the depletion of gate electrodes, replacement of gate material by a metal or metal silicide (metal gate) is considered. In particular, full replacement of the gate material, i.e., polycrystalline silicon, by a metal silicide (full silicidation) is attracting attention from the viewpoints of the thermal stability during the process of manufacturing the device and the cost of manufacturing the device.
A Fin-type channel transistor, which has a channel in a shape of plate standing on a substrate in a perpendicular manner, is a kind of multigate transistors, and called “Fin-type channel transistor” from its channel shape. It is highly of immunity to the short channel effect because of its strong gate dominance. In the ITRS, this type of transistor is explained in the chapter relating to Emerging Research Devices (Y. K. Choi et al. “FinFET Process Refinements for Improved Mobility and Gate Work Function Engineering”, Technical Digest of International Electron Devices Meeting (IEDM) (December 2002), page 259).
Thus, a Fin-type channel transistor has a structure very promising to deal with the short channel effect. However, because of the structural complication, there are the following three problems arising in the process of manufacturing a Fin-type channel transistor.
First, when an extension layer, a halo layer, and a deep region are formed by ion implantation, it is difficult to introduce the impurity under the target Fin because of the existence of adjacent Fins, which renders it difficult to control the impurity profile.
Second, when a gate sidewall is formed, the sidewall material may remain on the channel Fins, which may reduce the resistance-decreasing effect of the self-aligned silicide.
Third, since the thickness of polycrystalline silicon at the upper surface of Fins differs from the thickness thereof at the portions between adjacent Fins, the amount of a metal provided is determined by the thicker portion. As a result, a too much amount of the metal is provided to the portions, in which the thickness of polycrystalline silicon is thinner, some silicides may move over the gate sidewall during the silicidation process and may cause the bridging between gate and source/drain.
Due to the aforementioned problems in the manufacturing process, actual Fin-type channel transistors have problems in that the parasitic resistances vary, the device characteristics vary, and the heights of Fins cannot be increased to improve the drive current capability.